Sorting Accelerator on FPGA

CSE 293 - Verilog to Silicon

Arian Heidari, Sean Li, Gary Mejia, Mitchell Tansey

March 14, 2025

Overview of Project

Sorting algoritms are everywhere
- Sorting task by priority
- Sorting names in a roster
Simple enough to implement in software
- At best most sorts have an O(nlog(n)) runtime
- Can we do better in hardware?

Architecture

Use PicoRV32 softcore to load memory for external sorter core to sort on

Hardware - ULX3S Development Board

Specification

FPGA: Lattice ECP5
- LFE5U-85F-6BG381C (84 K LUT)
- LFE5U-45F-6BG381C (44 K LUT)
- LFE5U-12F-6BG381C (12 K LUT)
USB: FTDI FT231XS (500 kbit JTAG and 3 Mbit USB-serial)
RAM: 32 MB SDRAM 166 MHz
Flash: 4-16 MB Quad-SPI Flash for FPGA config and user data storage
LEDs: 11 (8 user LEDs, 2 USB LEDs, 1 Wi-Fi LED)
Buttons: 7 (4 direction, 2 fire, 1 power button)
Wi-Fi & Bluetooth: ESP32-WROOM-32 supports a standalone JTAG web interface over Wi-Fi

Tool Flow

YosysHQ’s OSS CAD Suite on Github Codespaces
- Yosys for Synthesis
- nextpnr-ecp5 for place and route
- ecppack for bitstream generation
- ecppll for PLL configuration
- fujproj/openFPGALoader for programming
- Verilator for simulation and linting
- GTKWave for waveform viewing

Components in Detail

PicoRV32

A Size-Optimized RISC-V CPU
- Supports RV32IMC Instruction Set
- Single Cycle
- AXI Lite Interface Supported
- PCPI Interface to interact with external cores
Available from YosysHQ’s picorv32 repo

Purpose of CPU

CPU is to load the sorter’s memory with integers
After sorter signals that it is done, CPU “prints” out the array
- CPU will just write to memory mapped IO to a UART module

Pico Co-Processor Interface

Checks this bus upon receiving an unsupported instruction
- Sends this instruction to the sorter to begin sorting
- Receives an instruction back to signal sorter is sorting or done
- Requires C code to inline an instruction for sorting instead of compiling a function
Created new instruction: 0x0x81FF8FB3
- rd,rs1 and are rs2 are all 1’s
- opcode is 0b0110011
  - same as all R type instructions in RISCV32IM
- Fucnction7 field is 0b1000000 instead of 0b0000001

Main C Program - Bubble Sort

#include "firmware/firmware.h"

#define ARRAY_SIZE 64
//array held in speacial mem section of ram
int arr[ARRAY_SIZE] __attribute__((section(".sorter_section")));

// Function to swap two integers
void swap(int* a, int* b) {
    int temp = *a;
    *a = *b;
    *b = temp;
}

void bubbleSort(int arr[], int n) {
    int i, j;
    for (i = 0; i < n - 1; i++) {
        for (j = 0; j < n - i - 1; j++) {
            if (arr[j] > arr[j + 1]) {
                swap(&arr[j], &arr[j + 1]);
            }
        }
    }
}

// Main function
void main() {
    print_str("Sorting 64 elements\n");
    for (int i = 0; i < ARRAY_SIZE; i++) {
        arr[i] = (ARRAY_SIZE - i);  // Reverse order for worst-case scenario
    }
    bubbleSort(arr, ARRAY_SIZE);
    //call the uart module here for all items in the
    print_str("Sorted the Array:\n");
    for(int i = 0; i < ARRAY_SIZE; i++) {
    print_dec(arr[i]);
    print_chr(',');
    }
    print_chr(']');
    asm volatile(".word 0x81FF8FB3");
    print_str("\nProgram Terminated...\n");
}

Library - “stdio.h”

#include "firmware.h"

#define OUTPORT 0x1100BEE0

void print_chr(char ch)
{
    *((volatile uint32_t*)OUTPORT) = ch;
}

void print_str(const char *p)
{
    while (*p != 0)
        *((volatile uint32_t*)OUTPORT) = *(p++);
}
void print_dec(unsigned int val)
{
    char buffer[10];
    char *p = buffer;
    while (val || p == buffer) {
        *(p++) = (int)(val % 10);
        val = (int)(val / 10);
    }
    while (p != buffer) {
        *((volatile uint32_t*)OUTPORT) = '0' + *(--p);
    }
}
void print_hex(unsigned int val, int digits)
{
    for (int i = (4*digits)-4; i >= 0; i -= 4)
        *((volatile uint32_t*)OUTPORT) = "0123456789ABCDEF"[(val >> i) % 16];
}

Bootloading and Compiler Infrastructure

Requires a basic bootloader
- Just an assembly file that sets all registers to 0, initializes SP, jumps to main and ebreak
- Uses RISCV32I GCC cross compiler
- Print functionality is memory mapped IO
- Custom Linker Script to denote memory regions of binary

Bootloader

start:
    addi x1, zero, 0
    addi x2, zero, 0
    addi x3, zero, 0
    addi x4, zero, 0
    addi x5, zero, 0
    addi x6, zero, 0
    addi x7, zero, 0
    addi x8, zero, 0
    addi x9, zero, 0
    addi x10, zero, 0
    addi x11, zero, 0
    addi x12, zero, 0
    addi x13, zero, 0
    addi x14, zero, 0
    addi x15, zero, 0
    addi x16, zero, 0
    addi x17, zero, 0
    addi x18, zero, 0
    addi x19, zero, 0
    addi x20, zero, 0
    addi x21, zero, 0
    addi x22, zero, 0
    addi x23, zero, 0
    addi x24, zero, 0
    addi x25, zero, 0
    addi x26, zero, 0
    addi x27, zero, 0
    addi x28, zero, 0
    addi x29, zero, 0
    addi x30, zero, 0
    addi x31, zero, 0
    /* set stack pointer */
    li sp,0x01005000
    /* call hello C code */
    jal main
    NOP
    ebreak

Memory Regions

MEMORY {
    code : ORIGIN = 0x00000000, LENGTH = 0x00001000
    main_mem : ORIGIN = 0x01001000, LENGTH = 0x00004000
    sorter_mem : ORIGIN = 0x10005000, LENGTH = 0x00004000
}

SECTIONS {
    .text :
    {
        . = ALIGN(4);
        *(.text)
        *(.text*)
        *(.rodata)
        *(.rodata*)
        *(.srodata)
        *(.srodata*)
        . = ALIGN(4);
        _etext = .;
        _sidata = _etext;
    } >code
    .data : AT ( 0x1000 )
    {
        . = ALIGN(4);
        _sdata = .;
        _ram_start = .;
        . = ALIGN(4);
        *(.data)
        *(.data*)
        *(.sdata)
        *(.sdata*)
        . = ALIGN(4);
        _edata = .;
    } >main_mem
    .bss :
    {
        . = ALIGN(4);
        _sbss = .;
        *(.bss)
        *(.bss*)
        *(.sbss)
        *(.sbss*)
        *(COMMON)
        . = ALIGN(4);
        _ebss = .;
    } >main_mem
    .sorter_section : AT ( 0x5000 )
    {
        KEEP(*(.sorter_section))
    } >sorter_mem
}

ELF Dump Contents

firmware/firmware.elf:     file format elf32-littleriscv


Disassembly of section .text:

00000000 <start>:
   0:   00000093            li  ra,0
   4:   00000113            li  sp,0
   8:   00000193            li  gp,0
   c:   00000213            li  tp,0
  10:   00000293            li  t0,0
  14:   00000313            li  t1,0
  18:   00000393            li  t2,0
  1c:   00000413            li  s0,0
  20:   00000493            li  s1,0
  24:   00000513            li  a0,0
  28:   00000593            li  a1,0
  2c:   00000613            li  a2,0
  30:   00000693            li  a3,0
  34:   00000713            li  a4,0
  38:   00000793            li  a5,0
  3c:   00000813            li  a6,0
  40:   00000893            li  a7,0
  44:   00000913            li  s2,0
  48:   00000993            li  s3,0
  4c:   00000a13            li  s4,0
  50:   00000a93            li  s5,0
  54:   00000b13            li  s6,0
  58:   00000b93            li  s7,0
  5c:   00000c13            li  s8,0
  60:   00000c93            li  s9,0
  64:   00000d13            li  s10,0
  68:   00000d93            li  s11,0
  6c:   00000e13            li  t3,0
  70:   00000e93            li  t4,0
  74:   00000f13            li  t5,0
  78:   00000f93            li  t6,0
  7c:   01005137            lui sp,0x1005
  80:   224000ef            jal ra,2a4 <main>
  84:   00000013            nop
  88:   00100073            ebreak

0000008c <print_chr>:
  8c:   1100c737            lui a4,0x1100c
  90:   eef70793            addi    a5,a4,-273 # 1100beef <arr+0x1006eef>
  94:   0ff57693            andi    a3,a0,255
  98:   eef74603            lbu a2,-273(a4)
  9c:   eed707a3            sb  a3,-273(a4)
  a0:   ef074703            lbu a4,-272(a4)
  a4:   000780a3            sb  zero,1(a5)
  a8:   0027c703            lbu a4,2(a5)
  ac:   00078123            sb  zero,2(a5)
  b0:   01855513            srli    a0,a0,0x18
  b4:   0037c703            lbu a4,3(a5)
  b8:   00a781a3            sb  a0,3(a5)
  bc:   00008067            ret

000000c0 <print_str>:
  c0:   00054703            lbu a4,0(a0)
  c4:   02070e63            beqz    a4,100 <print_str+0x40>
  c8:   1100c6b7            lui a3,0x1100c
  cc:   00150513            addi    a0,a0,1
  d0:   0ff77613            andi    a2,a4,255
  d4:   eef6c583            lbu a1,-273(a3) # 1100beef <arr+0x1006eef>
  d8:   eec687a3            sb  a2,-273(a3)
  dc:   ef06c603            lbu a2,-272(a3)
  e0:   ee068823            sb  zero,-272(a3)
  e4:   ef16c603            lbu a2,-271(a3)
  e8:   ee0688a3            sb  zero,-271(a3)
  ec:   01875713            srli    a4,a4,0x18
  f0:   ef26c603            lbu a2,-270(a3)
  f4:   eee68923            sb  a4,-270(a3)
  f8:   00054703            lbu a4,0(a0)
  fc:   fc0718e3            bnez    a4,cc <print_str+0xc>
 100:   00008067            ret

00000104 <print_dec>:
 104:   ff010113            addi    sp,sp,-16 # 1004ff0 <_edata+0x3ff0>
 108:   00410793            addi    a5,sp,4
 10c:   00078613            mv  a2,a5
 110:   00a00713            li  a4,10
 114:   0140006f            j   128 <print_dec+0x24>
 118:   00178793            addi    a5,a5,1
 11c:   02e576b3            remu    a3,a0,a4
 120:   fed78fa3            sb  a3,-1(a5)
 124:   02e55533            divu    a0,a0,a4
 128:   fe0518e3            bnez    a0,118 <print_dec+0x14>
 12c:   fec786e3            beq a5,a2,118 <print_dec+0x14>
 130:   1100c637            lui a2,0x1100c
 134:   00410513            addi    a0,sp,4
 138:   fff78793            addi    a5,a5,-1
 13c:   0007c703            lbu a4,0(a5)
 140:   03070713            addi    a4,a4,48
 144:   0ff77593            andi    a1,a4,255
 148:   eef64803            lbu a6,-273(a2) # 1100beef <arr+0x1006eef>
 14c:   eeb607a3            sb  a1,-273(a2)
 150:   00875593            srli    a1,a4,0x8
 154:   ef064803            lbu a6,-272(a2)
 158:   eeb60823            sb  a1,-272(a2)
 15c:   ef164583            lbu a1,-271(a2)
 160:   ee0608a3            sb  zero,-271(a2)
 164:   01875713            srli    a4,a4,0x18
 168:   ef264583            lbu a1,-270(a2)
 16c:   eee60923            sb  a4,-270(a2)
 170:   fca794e3            bne a5,a0,138 <print_dec+0x34>
 174:   01010113            addi    sp,sp,16
 178:   00008067            ret

0000017c <swap>:
 17c:   fd010113            addi    sp,sp,-48
 180:   02812623            sw  s0,44(sp)
 184:   03010413            addi    s0,sp,48
 188:   fca42e23            sw  a0,-36(s0)
 18c:   fcb42c23            sw  a1,-40(s0)
 190:   fdc42783            lw  a5,-36(s0)
 194:   0007a783            lw  a5,0(a5)
 198:   fef42623            sw  a5,-20(s0)
 19c:   fd842783            lw  a5,-40(s0)
 1a0:   0007a703            lw  a4,0(a5)
 1a4:   fdc42783            lw  a5,-36(s0)
 1a8:   00e7a023            sw  a4,0(a5)
 1ac:   fd842783            lw  a5,-40(s0)
 1b0:   fec42703            lw  a4,-20(s0)
 1b4:   00e7a023            sw  a4,0(a5)
 1b8:   00000013            nop
 1bc:   02c12403            lw  s0,44(sp)
 1c0:   03010113            addi    sp,sp,48
 1c4:   00008067            ret

000001c8 <bubbleSort>:
 1c8:   fd010113            addi    sp,sp,-48
 1cc:   02112623            sw  ra,44(sp)
 1d0:   02812423            sw  s0,40(sp)
 1d4:   03010413            addi    s0,sp,48
 1d8:   fca42e23            sw  a0,-36(s0)
 1dc:   fcb42c23            sw  a1,-40(s0)
 1e0:   fe042623            sw  zero,-20(s0)
 1e4:   09c0006f            j   280 <bubbleSort+0xb8>
 1e8:   fe042423            sw  zero,-24(s0)
 1ec:   0700006f            j   25c <bubbleSort+0x94>
 1f0:   fe842783            lw  a5,-24(s0)
 1f4:   00279793            slli    a5,a5,0x2
 1f8:   fdc42703            lw  a4,-36(s0)
 1fc:   00f707b3            add a5,a4,a5
 200:   0007a703            lw  a4,0(a5)
 204:   fe842783            lw  a5,-24(s0)
 208:   00178793            addi    a5,a5,1
 20c:   00279793            slli    a5,a5,0x2
 210:   fdc42683            lw  a3,-36(s0)
 214:   00f687b3            add a5,a3,a5
 218:   0007a783            lw  a5,0(a5)
 21c:   02e7da63            bge a5,a4,250 <bubbleSort+0x88>
 220:   fe842783            lw  a5,-24(s0)
 224:   00279793            slli    a5,a5,0x2
 228:   fdc42703            lw  a4,-36(s0)
 22c:   00f706b3            add a3,a4,a5
 230:   fe842783            lw  a5,-24(s0)
 234:   00178793            addi    a5,a5,1
 238:   00279793            slli    a5,a5,0x2
 23c:   fdc42703            lw  a4,-36(s0)
 240:   00f707b3            add a5,a4,a5
 244:   00078593            mv  a1,a5
 248:   00068513            mv  a0,a3
 24c:   f31ff0ef            jal ra,17c <swap>
 250:   fe842783            lw  a5,-24(s0)
 254:   00178793            addi    a5,a5,1
 258:   fef42423            sw  a5,-24(s0)
 25c:   fd842703            lw  a4,-40(s0)
 260:   fec42783            lw  a5,-20(s0)
 264:   40f707b3            sub a5,a4,a5
 268:   fff78793            addi    a5,a5,-1
 26c:   fe842703            lw  a4,-24(s0)
 270:   f8f740e3            blt a4,a5,1f0 <bubbleSort+0x28>
 274:   fec42783            lw  a5,-20(s0)
 278:   00178793            addi    a5,a5,1
 27c:   fef42623            sw  a5,-20(s0)
 280:   fd842783            lw  a5,-40(s0)
 284:   fff78793            addi    a5,a5,-1
 288:   fec42703            lw  a4,-20(s0)
 28c:   f4f74ee3            blt a4,a5,1e8 <bubbleSort+0x20>
 290:   00000013            nop
 294:   02c12083            lw  ra,44(sp)
 298:   02812403            lw  s0,40(sp)
 29c:   03010113            addi    sp,sp,48
 2a0:   00008067            ret

000002a4 <main>:
 2a4:   fe010113            addi    sp,sp,-32
 2a8:   00112e23            sw  ra,28(sp)
 2ac:   00812c23            sw  s0,24(sp)
 2b0:   02010413            addi    s0,sp,32
 2b4:   fe042623            sw  zero,-20(s0)
 2b8:   0340006f            j   2ec <main+0x48>
 2bc:   00001737            lui a4,0x1
 2c0:   fec42783            lw  a5,-20(s0)
 2c4:   40f70733            sub a4,a4,a5
 2c8:   100057b7            lui a5,0x10005
 2cc:   fec42683            lw  a3,-20(s0)
 2d0:   00269693            slli    a3,a3,0x2
 2d4:   00078793            mv  a5,a5
 2d8:   00f687b3            add a5,a3,a5
 2dc:   00e7a023            sw  a4,0(a5) # 10005000 <arr>
 2e0:   fec42783            lw  a5,-20(s0)
 2e4:   00178793            addi    a5,a5,1
 2e8:   fef42623            sw  a5,-20(s0)
 2ec:   fec42703            lw  a4,-20(s0)
 2f0:   000017b7            lui a5,0x1
 2f4:   fcf744e3            blt a4,a5,2bc <main+0x18>
 2f8:   000015b7            lui a1,0x1
 2fc:   100057b7            lui a5,0x10005
 300:   00078513            mv  a0,a5
 304:   ec5ff0ef            jal ra,1c8 <bubbleSort>
 308:   00000013            nop
 30c:   01c12083            lw  ra,28(sp)
 310:   01812403            lw  s0,24(sp)
 314:   02010113            addi    sp,sp,32
 318:   00008067            ret

Sorter

Has both PCPI and AXI Lite interfaces
Accepts data from sorting memory until local memory is full, sorts local memory, then returns the sorted output in from largest to smallest

Abstracting For Loops and Cycle Delays

Some familiar statements are unsuitable for HDL:
- For loops are unideal as they replicate the code block, which become increasingly intensive as the range increases
- Local memory accesses are done in a pipeline (utilizing Ethan’s pipelined_mem.sv), and are available only after 2 clock cycles
Counters act as an effective abstraction of for loops and delays, without encountering the corresponding pitfalls

Sorting RTL

For Loop Example:

always_comb begin
    for_i_addr_d = for_i_addr_q;
    for_j_addr_d = for_j_addr_q;

    if (for_i_addr_d != (DATA_ENTRIES) && (i_en)) begin
        if (for_j_addr_q != (DATA_ENTRIES-1) && (j_en)) begin
            if (for_j_addr_q < for_i_addr_q) begin // New BS Line
                for_j_addr_d = for_i_addr_q + 1;
            end else begin
                for_j_addr_d = for_j_addr_q + 1;
            end
        end else begin
            if (for_i_addr_q == (DATA_ENTRIES - 1))
                for_i_addr_d = '0;
            else
                for_i_addr_d = for_i_addr_q + 1;
            if ((for_i_addr_q + 2) == (DATA_ENTRIES)) begin
                for_j_addr_d = for_i_addr_q + 1;
            end else if ((for_i_addr_q + 1) == (DATA_ENTRIES)) begin
                for_j_addr_d = '0;
            end else begin
                for_j_addr_d = for_i_addr_q + 2;
            end
        end
    end else begin
        for_i_addr_d = for_i_addr_q;
        for_j_addr_d = for_j_addr_q;
    end
end

Sorter Simulations

Sorter Output Simulation

Memory

AXI Lite RAM

Taken from Alex Forencich’s verilog-axi repo
Standard RAM module with AXI Lite signal handling
- This handles proper communication of memory from Pico
Used for general CPU main memory and shared sorter memory

AXI Lite ROM

Modified AXI Lite RAM module to use $readmemh function
Acts as instruction memory for the Pico
Does not synthesize to BRAM on ECP5

Communication

AXI Stream FIFO

Taken from Alex Forencich’s verilog-axis repo
Acts as the stdout buffer
Since it is AXI Stream it can not give backpressure to the CPU
- As a result we do not know the maximum about of chars the fifo can hold

AXI Lite UART Module

Taken from Alex Forencich’s verilog-uart repo
AXI Stream interface that directly interfaces with the stdout buffer FIFO
Acts as stdout for our design

AXI Lite Interconnect

Taken from Alex Forencich’s verilog-axi repo
Act as a multiplexor or demultiplexor for AXI Lite signals
Pico communications with 3 different AXI Lite Peripherals
- This requires a 1 to 3 Interconnect
Sorter RAM has two different users - sorter and Pico
- This requires a 2 to 1 Interconnect
Provided Python script generates the appriopriate wrapper module for each use case

Outcomes

Verification

task run_until_ebreak;
    while (~|led[7:6]) begin
        @(posedge clk_i);
    end
    if (led[7]) begin
        peek_memory_bus();
        $error("Trap is illegally found!");
    end else begin
        $info("Ebreak found, main is returning/terminating properly");
        @(posedge clk_i); //simulate one more cycle to see the proper trap behavior
    end
endtask

Specifications

Max Clock Frequency - 75.30MHz
- We run at 50MHz
Memories are at 16KB
- FIFO has a capicity of 256B
Sorter not yet implemented due to time constraints
- Sorts 64 elements

Ulitization Report

Info: Device utilisation:
Info:             TRELLIS_IO:      11/    365     3%
Info:                   DCCA:       1/     56     1%
Info:                 DP16KD:      97/    208    46%
Info:             MULT18X18D:       0/    156     0%
Info:                 ALU54B:       0/     78     0%
Info:                EHXPLLL:       1/      4    25%
Info:                EXTREFB:       0/      2     0%
Info:                   DCUA:       0/      2     0%
Info:              PCSCLKDIV:       0/      2     0%
Info:                IOLOGIC:       0/    224     0%
Info:               SIOLOGIC:       0/    141     0%
Info:                    GSR:       0/      1     0%
Info:                  JTAGG:       0/      1     0%
Info:                   OSCG:       0/      1     0%
Info:                  SEDGA:       0/      1     0%
Info:                    DTR:       0/      1     0%
Info:                USRMCLK:       0/      1     0%
Info:                CLKDIVF:       0/      4     0%
Info:              ECLKSYNCB:       0/     10     0%
Info:                DLLDELD:       0/      8     0%
Info:                 DDRDLL:       0/      4     0%
Info:                DQSBUFM:       0/     14     0%
Info:        TRELLIS_ECLKBUF:       0/      8     0%
Info:           ECLKBRIDGECS:       0/      2     0%
Info:                   DCSC:       0/      2     0%
Info:             TRELLIS_FF:    1324/  83640     1%
Info:           TRELLIS_COMB:    3448/  83640     4%
Info:           TRELLIS_RAMW:      32/  10455     0%

Slack Histogram

Info: Slack histogram:
Info:  legend: * represents 11 endpoint(s)
Info:          + represents [1,11) endpoint(s)
Info: [  6719,   7336) |+
Info: [  7336,   7953) |+
Info: [  7953,   8570) |+
Info: [  8570,   9187) |*+
Info: [  9187,   9804) |*+
Info: [  9804,  10421) |*+
Info: [ 10421,  11038) |**+
Info: [ 11038,  11655) |************+
Info: [ 11655,  12272) |*************+
Info: [ 12272,  12889) |**********+
Info: [ 12889,  13506) |*****************+
Info: [ 13506,  14123) |******************************+
Info: [ 14123,  14740) |******************************+
Info: [ 14740,  15357) |**************************************+
Info: [ 15357,  15974) |****************************************************+
Info: [ 15974,  16591) |************************************************************
Info: [ 16591,  17208) |************************************************+
Info: [ 17208,  17825) |******************************************************+
Info: [ 17825,  18442) |***********************+
Info: [ 18442,  19059) |*********+

Challenges

Sorter

Creating a sorting algorithm without for loops, function calls, or direct array manipulation
- Incomplete conditions between for loops and sorter
Timing between state machine and pipelined memory
Read validity for sorting algorithm
Data validity for AXIL
Termination of states too early
Memory overwriting itself with ’x
Pipelined memory read/write calls; read_valid_o and request_valid_i
AXIL Interface (overlapping vs mutually exclusive signals)

Original Design

ESP32 as hardcore with SDRAM as shared memory, AXI Stream as main communication interface

Why ESP32 Failed

Requires either a vendor specific bitstream and passthru logic to bypass the FTDI chip from programming the FPGA and target the ESP32
- This is required as there is only 1 FTDI chip onboard
- Documentation hazy on whether this another IP or required to be our top module
Unclear which pins are even connected to the FPGA to use for UART communication between the ESP32
ESP-IDF does not seem to target the ESP32 but the Arduino IDE does
- Unclear if the Arduino Serial library is using the pins we want

Passthru RTL - VHDL

-- (c)EMARD
-- License=BSD

-- module to bypass user input and usbserial to esp32 wifi

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use work.f32c_pack.all;

library ecp5u;
use ecp5u.components.all;

entity ulx3s_passthru_wifi is
  generic
  (
    C_dummy_constant: integer := 0
  );
  port
  (
  clk_25mhz: in std_logic;  -- main clock input from 25MHz clock source must be lowercase

  -- UART0 (FTDI USB slave serial)
  ftdi_rxd: out   std_logic;
  ftdi_txd: in    std_logic;
  -- FTDI additional signaling
  ftdi_ndtr: inout  std_logic;
  ftdi_ndsr: inout  std_logic;
  ftdi_nrts: inout  std_logic;
  ftdi_txden: inout std_logic;

  -- UART1 (WiFi serial)
  wifi_rxd: out   std_logic;
  wifi_txd: in    std_logic;
  -- WiFi additional signaling
  wifi_en, wifi_gpio0, wifi_gpio2, wifi_gpio5, wifi_gpio16, wifi_gpio17: inout  std_logic := 'Z'; -- '0' will disable wifi by default

  -- Onboard blinky
  led: out std_logic_vector(7 downto 0);
  btn: in std_logic_vector(6 downto 0);
  sw: in std_logic_vector(0 to 3);
  oled_csn, oled_clk, oled_mosi, oled_dc, oled_resn: out std_logic;

  -- GPIO (some are shared with wifi and adc)
  gp, gn: inout std_logic_vector(27 downto 0) := (others => 'Z');

  -- SHUTDOWN: logic '1' here will shutdown power on PCB >= v1.7.5
  shutdown: out std_logic := '0';

  -- Audio jack 3.5mm
  audio_l, audio_r, audio_v: inout std_logic_vector(3 downto 0) := (others => 'Z');

  -- Digital Video (differential outputs)
  --gpdi_dp, gpdi_dn: out std_logic_vector(2 downto 0);
  --gpdi_clkp, gpdi_clkn: out std_logic;

  -- Flash ROM (SPI0)
  --flash_miso   : in      std_logic;
  --flash_mosi   : out     std_logic;
  --flash_clk    : out     std_logic;
  --flash_csn    : out     std_logic;
  flash_holdn, flash_wpn: out std_logic := '1';

  -- SD card (SPI1)
  sd_d: inout std_logic_vector(3 downto 0); -- wifi_gpio 13,12,4,2
  sd_cmd: in std_logic; -- wifi_gpio15
  sd_clk: in std_logic; -- wifi_gpio14
  sd_cdn, sd_wp: in std_logic;

  user_programn: out std_logic -- setting this low will skip to next multiboot image
  );
end;

architecture Behavioral of ulx3s_passthru_wifi is
  signal S_prog_in, R_prog_in, S_prog_out: std_logic_vector(1 downto 0);
  signal R_spi_miso: std_logic_vector(7 downto 0);
  signal S_oled_csn: std_logic;
  constant C_prog_release_timeout: integer := 17; -- default 17 2^n * 25MHz timeout for initialization phase
  signal R_prog_release: std_logic_vector(C_prog_release_timeout downto 0) := (others => '1'); -- timeout that holds lines for reliable entering programming mode
  signal R_progn: std_logic_vector(7 downto 0) := (others => '0');
begin

  -- TX/RX passthru
--  ftdi_rxd <= wifi_txd;
--  wifi_rxd <= ftdi_txd;

  ftdi_rxd <= wifi_txd when sw(0)='1' else wifi_gpio17;
  wifi_rxd <= ftdi_txd when sw(0)='1' else '1';
  wifi_gpio16 <=   '1' when sw(0)='1' else ftdi_txd;

  -- Programming logic
  -- SERIAL  ->  ESP32
  -- DTR RTS -> EN IO0
  --  1   1     1   1
  --  0   0     1   1
  --  1   0     0   1
  --  0   1     1   0
  S_prog_in(1) <= ftdi_ndtr;
  S_prog_in(0) <= ftdi_nrts;
  S_prog_out <= "01" when S_prog_in = "10" else
                "10" when S_prog_in = "01" else
                "11";
  wifi_en <= S_prog_out(1);
  wifi_gpio0 <= S_prog_out(0) and btn(0); -- holding BTN0 will hold gpio0 LOW, signal for ESP32 to take control
  --sd_d(0) <= '0' when wifi_gpio0 = '0' else 'Z'; -- gpio2 together with gpio0 to 0
  --sd_d(2) <= '0' when wifi_gpio0 = '0' else 'Z'; -- wifi gpio12
  sd_d(0) <= S_prog_out(0) when R_prog_release(R_prog_release'high) = '0' else
             -- '1' when R_prog_release(R_prog_release'high) = '0' else
             R_spi_miso(0) when S_oled_csn = '0' else -- SPI reading buttons with OLED CSn
             'Z'; -- gpio2 to 0 during programming init
  -- sd_d(2) <= '0' when (S_prog_in(0) xor S_prog_in(1)) = '1' else 'Z'; -- wifi gpio12
  -- sd_d(2) <= '0' when R_prog_release(R_prog_release'high) = '0' else 'Z'; -- wifi gpio12
  -- sd_d(3) <= '1' when R_prog_release(R_prog_release'high) = '0' else 'Z';
  -- sd_clk <= clk_25mhz when R_prog_release(R_prog_release'high) = '0' else 'Z';
  -- permanent flashing mode
  -- wifi_en <= ftdi_nrts;
  -- wifi_gpio0 <= ftdi_ndtr;

  S_oled_csn <= '1'; -- wifi_gpio17;
  oled_csn <= S_oled_csn;
  oled_clk <= sd_clk; -- wifi_gpio14
  oled_mosi <= sd_cmd; -- wifi_gpio15
  oled_dc <= '1'; -- wifi_gpio16;
  oled_resn <= gp(11); -- wifi_gpio25

  -- show OLED signals on the LEDs
  -- show SD signals on the LEDs
  -- led(7 downto 0) <= S_oled_csn & R_spi_miso(0) & sd_clk & sd_d(2) & sd_d(3) & sd_cmd & sd_d(0) & sd_d(1); -- beautiful but makes core unreliable
  led(7) <= wifi_gpio5; -- for boards without D22 soldered
  led(6) <= S_prog_out(1); -- green LED indicates ESP32 disabled
  led(5) <= not R_prog_release(R_prog_release'high); -- ESP32 programming start: blinks too short to be visible
  --led(3) <= sd_d(3); -- sd_d(3) is sd_cs, pullup=NONE in constraints otherwise SD card will prevents esp32 from entering programming mode...
  --led(2) <= sd_d(2);
  --led(1) <= sd_d(1);
  --led(0) <= sd_d(0);

  -- programming release counter
  process(clk_25MHz)
  begin
      if rising_edge(clk_25MHz) then
        R_prog_in <= S_prog_in;
        if S_prog_out = "01" and R_prog_in = "11" then
          R_prog_release <= (others => '0');
        else
          if R_prog_release(R_prog_release'high) = '0' then
            R_prog_release <= R_prog_release + 1;
          end if;
        end if;
      end if;
  end process;

  -- if user presses BTN0 and BTN1 then pull down PROGRAMN for multiboot
  process(clk_25MHz)
  begin
    if rising_edge(clk_25MHz) then
      if btn(0) = '0' and btn(1) = '1' then
        R_progn <= R_progn + 1; -- BTN0 BTN1 are pressed
      else
        R_progn <= (others => '0'); -- BTN0 BTN1 are not pressed
      end if;
    end if;
  end process;
  user_programn <= not R_progn(R_progn'high);

end Behavioral;

Passthru RTL - Verilog

// (c)EMARD
// License=BSD

// Module to bypass user input and USB serial to ESP32 WiFi

module ulx3s (
    input wire clk_25mhz,  // Main clock input (25MHz)
    input wire reset_ni,

    // UART0 (FTDI USB slave serial)
    output reg ftdi_rxd,
    input wire ftdi_txd,

    // FTDI additional signaling
    inout wire ftdi_ndtr,
    // inout wire ftdi_ndsr,
    inout wire ftdi_nrts,
    inout wire ftdi_txden,

    // UART1 (WiFi serial)
    output reg wifi_rxd,
    input wire wifi_txd,

    // WiFi additional signaling
    inout wire wifi_en,
    inout wire wifi_gpio0,
    // inout wire wifi_gpio2,
    inout wire wifi_gpio5,
    inout wire wifi_gpio16,
    inout wire wifi_gpio17,

    // Onboard blinky
    output reg [7:0] led,
    input wire [6:1] btn,
    input wire [3:0] sw,
    output reg oled_csn,
    output reg oled_clk,
    output reg oled_mosi,
    output reg oled_dc,
    output reg oled_resn,

    // GPIO (some shared with WiFi and ADC)
    inout wire [27:0] gp,
    inout wire [27:0] gn,

    // SHUTDOWN: logic '1' here will shut down power on PCB >= v1.7.5
    output reg shutdown,

    // Audio jack 3.5mm
    inout wire [3:0] audio_l,
    inout wire [3:0] audio_r,
    inout wire [3:0] audio_v,

    // Flash ROM (SPI0)
    output reg flash_holdn,
    output reg flash_wpn,

    // SD card (SPI1)
    inout wire [3:0] sd_d,
    input wire sd_cmd,  // WiFi GPIO15
    input wire sd_clk,  // WiFi GPIO14
    input wire sd_cdn,
    input wire sd_wp,

    output reg user_programn // setting this low will skip to next multiboot image
);

// Internal registers
reg [1:0] S_prog_in, R_prog_in, S_prog_out;
reg [7:0] R_spi_miso;
reg S_oled_csn;
reg [17:0] R_prog_release; // Timeout counter
reg [7:0] R_progn;

// TX/RX passthru logic
always @(*) begin
    ftdi_rxd = wifi_txd;
end

// Programming logic
always @(*) begin
    S_prog_in = {ftdi_ndtr, ftdi_nrts};
    case (S_prog_in)
        2'b10: S_prog_out = 2'b01;
        2'b01: S_prog_out = 2'b10;
        default: S_prog_out = 2'b11;
    endcase

    wifi_en = S_prog_out[1];
    wifi_gpio0 = S_prog_out[0] & btn[0]; // Hold BTN0 to keep gpio0 LOW
    sd_d[0] = (R_prog_release[17] == 0) ? S_prog_out[0] : 1'bz;
end

// OLED connection
always @(*) begin
    S_oled_csn = 1;
    oled_csn = S_oled_csn;
    oled_clk = sd_clk;
    oled_mosi = sd_cmd;
    oled_dc = 1;
    oled_resn = gp[11];
end

// LED control signals
always @(*) begin
    led[7] = wifi_gpio5;
    led[6] = S_prog_out[1]; // Green LED when ESP32 disabled
    led[5] = ~R_prog_release[17]; // Indicate ESP32 programming start
end

// Programming release counter
always @(posedge clk_25mhz) begin
    R_prog_in <= S_prog_in;
    if (S_prog_out == 2'b01 && R_prog_in == 2'b11) begin
        R_prog_release <= 0;
    end else if (R_prog_release[17] == 0) begin
        R_prog_release <= R_prog_release + 1;
    end
end

// Multiboot selection via button press
always @(posedge clk_25mhz) begin
    if (btn[0] == 0 && btn[1] == 1) begin
        R_progn <= R_progn + 1;
    end else begin
        R_progn <= 0;
    end
end

wire clk;

(* FREQUENCY_PIN_CLKI="25" *)
(* FREQUENCY_PIN_CLKOP="32.256" *)
(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
EHXPLLL #(
        .PLLRST_ENA("DISABLED"),
        .INTFB_WAKE("DISABLED"),
        .STDBY_ENABLE("DISABLED"),
        .DPHASE_SOURCE("DISABLED"),
        .OUTDIVIDER_MUXA("DIVA"),
        .OUTDIVIDER_MUXB("DIVB"),
        .OUTDIVIDER_MUXC("DIVC"),
        .OUTDIVIDER_MUXD("DIVD"),
        .CLKI_DIV(7),               //Refclk divisor
        .CLKOP_ENABLE("ENABLED"),
        .CLKOP_DIV(19),              //clkout0 divisor
        .CLKOP_CPHASE(2),
        .CLKOP_FPHASE(0),
        .FEEDBK_PATH("CLKOP"),
        .CLKFB_DIV(9)   //Feedback Divisor
    ) pll (
        .RST(1'b0),
        .STDBY(1'b0),
        .CLKI(clk_25mhz),
        .CLKOP(clk),
        .CLKFB(clk),
        .CLKINTFB(),
        .PHASESEL0(1'b0),
        .PHASESEL1(1'b0),
        .PHASEDIR(1'b1),
        .PHASESTEP(1'b1),
        .PHASELOADREG(1'b1),
        .PLLWAKESYNC(1'b0),
        .ENCLKOP(1'b0),
        .LOCK(locked)
    );

top top_inst (.clk(clk), .rst(!reset_ni), .rx_i(ftdi_rxd), .tx_o(ftdi_txd));

assign led[2] = !ftdi_rxd;
assign led[4] = !sw[0];
assign led[5] = 1;
// assign led[2] = !btn[0];
// assign wifi_en = 1;
assign user_programn = ~R_progn[7];

endmodule

Why AXI Stream Failed

Memories are not streamable targets
AXI Stream has no destination
- The other end of the wire is the destination
With a read and write port it is unclear who asserts ready
AXI Lite scales better due to interconnect support
- Want to add another module? -> Just make a new address for it

Why SDRAM Failed

Specifications for SDRAM configurations were vague and inconsistent
Would require a CDC FIFO for safe data transfer to and from PicoRV32
Would have to add on AXI Lite to interface with most components of the system
Verification difficulties
- Verilog models are available for the specific memory but require industry tools to run as these are protected Verilog files (.vp)
- Simulated using Cadence Xcelium

Verilog Protected File Example

/***********************************************************************************************
|*Company             : Winbond Electronics Corp. ("WINBOND")
|*Model Type          : Verilog Model
|*Product             : SDRAM
|*Part Number         : W9825G6KH
|*Memory spec         : 4M x 4 Banks x 16 Bits
|*CAS Latency option  : CL2, CL3
|*AC Characteristics  : -5,-6I-6J-6L,-75-75J-75L
|*Burst Length option : BL1, BL2,BL4, BL8, full page
|$Revision            : 2.1
|$Date                : 2016/9/7
|                     : 2022/9/6
|                     : 2022/9/20
|*Revision History    : 1.0: Initial creation
|                     :    : a. To add the Debug flag for message display
|                     :      b. To modify the Dq_reg
|                     :
|                     :      add the Debug falg for all display
|                     : 2.0 : To make the model to be a general model
|                     : 2.1 : to change trrd checking from time to clk cntr
|*notes               : The generated from golden model
|*release date        : 2022_11_09
***********************************************************************************************
|*Disclaimer :
|This model software code and all related notes or documentation (collectively "Software") is
|provided "AS IS" without warranty of any kind. You bear the risk of using it.
|Winbond Electronics Corp.("WINBOND") hereunder DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED,
|INCLUDING BUT NOT LIMITED TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
|OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. WINBOND DOES NOT WARRANT THAT THE
|OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. FURTHERMORE, WINBOND DOES NOT MAKE
|ANY WARRANTIES REGARDING THE USE OR THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS
|CORRECTNESS, ACCURACY, RELIABILITY, OR OTHERWISE. IN NO EVENT SHALL WINBOND, ITS SUBSIDIARY
|COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, INCIDENTAL,
|OR SPECIAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
|BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE THE
|SOFTWARE, EVEN IF WINBOND HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
|*Copyright :
|Copyright C 2022 Winbond Electronics Corp. All rights reserved.°®
***********************************************************************************************/

/**********************************************************************************************
|     file structure:
|       include: Config-AC.v (file that contains all AC/DC parameters used by the model)
|       Codes  : protected Verilog model file by ncverilog   DRAM functions and IO timing checking
**********************************************************************************************/


/**********************************************************************************************
|Getting Started to use the model:
|
|
|Defining the SPEC. Grade:
|----------------------------
| You have to simulate with NC-Verilog compiler.
| If you want to simulate verilog behavioral model,
|
|   - Speed , Please comfirm with our Datasheet to define your condition.
|       -5,-6I-6J-6L,-75-75J-75L
|
|       For Example , if your sample is -6 and running under CL=3 , set condition as below...
|       -6 CL3      ( 6.0ns@CL3  )  ->   +T6CL3
|
|       For Example , if your sample is -6 and running under CL=2 , set condition as below...
|       -6 CL2      ( 10ns@CL2  )   ->   +T6CL2
|
|       others situation refer to above descrption.
|
|   - Burst Length
|       BL = 1      ->  BL1
|       BL = 2      ->  BL2
|       BL = 4      ->  BL4
|       BL = 8      ->  BL8
|
| EX} ncverilog +access+rwc +define+T6CL3+BL4 W9825G6KH.nc.vp W9825G6KH_sim.v
|
|   ( Please refer to datasheet and select the correct one which you want ... )
| then set following option(+define) for products in verilog command line.
|
|
**********************************************************************************************/


`timescale 1ns / 1ps

module W9825G6KH (
    Dq,
    Addr,
    Bs,
    Clk,
    Cke,
    Cs_n,
    Ras_n,
    Cas_n,
    We_n,
    Dqm
    );


`include "Config-AC.v"

    inout     [data_bits - 1 : 0] Dq;
    input     [row_bits - 1 : 0]  Addr;  //Address for tRC
    input                  [1 : 0] Bs;    //bank select
    input                          Clk;
    input                          Cke;
    input                          Cs_n;
    input                          Ras_n;
    input                          Cas_n;
    input                          We_n;
    input            [dm_bits-1 :0] Dqm;



    reg       [data_bits - 1 : 0] Bank0 [0 : mem_sizes-1];
    reg       [data_bits - 1 : 0] Bank1 [0 : mem_sizes-1];
    reg       [data_bits - 1 : 0] Bank2 [0 : mem_sizes-1];
    reg       [data_bits - 1 : 0] Bank3 [0 : mem_sizes-1];

    reg                    [1 : 0] Bank_addr [0:3];        // Bank Address
    reg        [col_bits - 1 : 0] Col_addr  [0:3];        // Column Address
    reg                    [3:0]   cmd [0:3];              // cmd Operation
    reg                    [dm_bits-1:0]   Dqm_reg0, Dqm_reg1;     // DQM Operation
    reg       [row_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;

    reg       [mode_addr_bits - 1 : 0] Mode_reg;
    reg       [data_bits - 1 : 0] Dq_reg, Dq_dqm;
    reg        [col_bits - 1 : 0] Col_temp, Burst_cnt;

    reg       Act_b0, Act_b1, Act_b2, Act_b3;   // Bank Activate
    reg       Pc_b0, Pc_b1, Pc_b2, Pc_b3;       // Bank Precharge

    reg         [1:0]   Bank_prech     [0:3];   // Precharge cmd
    reg                 A10_prech      [0:3];   // Addr[10] = 1 (All banks)
    reg                 Auto_prech     [0:3];   // RW Auto Precharge (Bank)
    reg                 RD_prech       [0:3];   // R  Auto Precharge
    reg                 WR_prech       [0:3];   // W  Auto Precharge
    reg                 RW_INT_rd      [0:3];   // RW Interrupt Read with Auto Precharge
    reg                 RW_INT_wr      [0:3];   // RW Interrupt Write with Auto Precharge
    reg         [1:0]   RW_INT_bank         ;   // RW Interrupt Bank

    integer RW_INT_cnt [3:0];   // RW Interrupt Counter
    integer prech_cnt  [3:0];   // RW Auto Precharge Counter
    integer MRD_chk;            // MRS to next command Counter

    reg     Din_en;
    reg     Din_en_chk;
    reg     Dout_en;
    reg     [1:0] Bank, Prev_bank;
    reg     [row_bits - 1 : 0] Row;
    reg     [col_bits - 1 : 0] Col, Col_brst;
// Internal system clock
    reg   CkeZ, Sys_clk;
    reg    dout_hiz_flag;


//pragma protect begin_protected
//pragma protect key_keyowner=Cadence Design Systems.
//pragma protect key_keyname=CDS_KEY
//pragma protect key_method=RC5
//pragma protect key_block
ZvjUzL2AJ4ZLbo69xbIzRwaqlDhEVowBfZVq3qRmB/obMKFLbJVHA5SvDfMxXYNS
f9kEdJuC5pxo9+ln2YKX3po3nuBJojCuzqU0AqAuuRoI1O4cBet0/bwN/qjNtXPG
FSNUZWXjazMa1fjMFQ4oYddRjq969SPFNmvAc30cyCNEcFfoFoSNhw==
//pragma protect end_key_block
//pragma protect digest_block
CYv/0RXkKPdNlH8uNxd997xwP2Y=
//pragma protect end_digest_block
//pragma protect data_block
XqFB58lqSIkJHWghQR3zI3EyDqtwGEZ+bI/gsNgO9toQUkLiv/gtZi0bWSxXLpaq
sJJuMusEJO8BmnVXvxOh7DCfA8p3bpOD1xRg7fnbhRxDVyYjjBSLh8W0C1FSZVM8
ZpI7PCz9s5cu0Ppk2fn0na4tpfJEdm1UjLcBi44nbR44Ff0Ykqp+sRX1KEBZSeC6
DEGkQucI3Q/9O4/JYYwVtFp1MAgc3k/w9gaKEczj+LOXBii8M3kAZC5ZP3HSoF/G
G0Oby/7W/CooSoVG3SOLcLMvhw5GBwVv2YkFp87IinmQe7HPmGHZK5XKtXCB/yup
p76un3yvwe3BT+gT5VssqIY4x+Yy5mj98CacKUeI9+Ll93dtPH534NGmosadtODl
vdKkDuF0N6wVt/u70D1WJpJtWxo8vTKyD0q0ysThtFu+5jKd9aS3XyeQmYKnESbb
VI4zqV6cwo4LdcNYQO2noGKN/WDLMibt4tP/baqjP9yeAN7n6J5bz4nlk+47NETR
DfWw5Vu5D48zf6/duSbi8VRJAKZ18o5ohiqqfmRfxmcARyl+tAeWdz0dLWqzVY5h
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wB7EP25iRNQ8rWGnqhFf+Q==
//pragma protect end_data_block
//pragma protect digest_block
NGeyEkLIL8si75TYcU4GouuEhNI=
//pragma protect end_digest_block
//pragma protect end_protected
endmodule

Config File

`define   X16


`ifdef X8
parameter  data_bits =         8        ;        // DQ I/Os
`endif

`ifdef X16
parameter  data_bits =         16       ;        // DQ I/Os
`endif


`ifdef X32
parameter  data_bits =         32       ;        // DQ I/Os
`endif


parameter  ba_bits          =    2;
parameter  mode_addr_bits   =    11;
parameter  dm_bits          =    data_bits/8;


parameter  row_bits =         13;        // Address Input
parameter  col_bits  =        9;
parameter  mem_sizes =      4194304;

parameter   tRRD_tck = 2; //tck
parameter   tRSC_tck = 2; //tck

`ifdef T5CL2
// Timing Parameters
parameter   tCK         = 10        ;   // Clock Cycle Time
parameter   tRC         = 55            ;// Ref/Act to Ref/Act Command Period
parameter   tRAS    = 40            ;// Active to Precharge Command Period
parameter   tRCD    = 15            ;// Active to Read/Write Command Delay Time
parameter   tCCD    = tCK       ;// Read/Write to Read/Write ( With different Bank) Command Period
parameter   tRP         = 15            ;// Precharge to Active Command Period
parameter   tWR     = 2*tCK ;   // Write Recovery Time
parameter   tCH     = 2         ;// Clock High-Level Width
parameter   tCL         = 2         ;// Clock Low-Level Width
parameter   tAC         = 6         ;// Access Time from CLK
parameter   tOH     = 3         ;// Output Data Hold Time
parameter   tHZ     = 6.0       ;   // Output Data High Impedance Time Max
parameter   tLZ         = 0         ;// Output Data Low Impedance Time
parameter   tSB_min = 0         ;// Power Down Mode Entry Time Min
parameter   tSB_max = 5         ;// Power Down Mode Entry Time Max
parameter   tDS         = 1.5     ;     // Data-in Setup Time
parameter   tDH     = 1.0   ;   // Data-in Hold Time
parameter   tAS         = 1.5     ;     // Addr, Bs Setup Time
parameter   tAH         = 1.0     ;     // Addr, Bs Hold Time
parameter   tCKS    = 1.5     ;     // CKE Setup Time
parameter   tCKH    = 1.0     ;     // CKE Hold  Time
parameter   tCMS    = 1.5     ;     // Command Setup Time
parameter   tCMH    = 1.0       ;   // Command Hold  Time
parameter   tREF    = 64000000; // Refresh Time
parameter   tRSC    = 2*tCK ;       // 2 * tCK
parameter   tWRa    = tWR     ; // Auto precharge mode
parameter   tWRm    = tWR     ; // Manual precharge mode
parameter   tXSR    = 70          ; // Exit self refresh to ACTIVE command
parameter   CL      = 2         ;// CAS Latency
`endif

`ifdef T5CL3
// Timing Parameters
parameter   tCK         =5.0      ;     // Clock Cycle Time
parameter   tRC         = 55            ;// Ref/Act to Ref/Act Command Period
parameter   tRAS    = 40            ;// Active to Precharge Command Period
parameter   tRCD    = 15            ;// Active to Read/Write Command Delay Time
parameter   tCCD    = tCK       ;// Read/Write to Read/Write ( With different Bank) Command Period
parameter   tRP         = 15            ;// Precharge to Active Command Period
parameter   tWR     = 2*tCK ;   // Write Recovery Time
parameter   tCH     = 2         ;// Clock High-Level Width
parameter   tCL         = 2         ;// Clock Low-Level Width
parameter   tAC         = 4.5           ;// Access Time from CLK
parameter   tOH     = 3         ;// Output Data Hold Time
parameter   tHZ     = 4.5       ;   // Output Data High Impedance Time Max
parameter   tLZ         = 0         ;// Output Data Low Impedance Time
parameter   tSB_min = 0         ;// Power Down Mode Entry Time Min
parameter   tSB_max = 5         ;// Power Down Mode Entry Time Max
parameter   tDS         = 1.5     ;     // Data-in Setup Time
parameter   tDH     = 1.0   ;   // Data-in Hold Time
parameter   tAS         = 1.5     ;     // Addr, Bs Setup Time
parameter   tAH         = 1.0     ;     // Addr, Bs Hold Time
parameter   tCKS    = 1.5     ;     // CKE Setup Time
parameter   tCKH    = 1.0     ;     // CKE Hold  Time
parameter   tCMS    = 1.5     ;     // Command Setup Time
parameter   tCMH    = 1.0       ;   // Command Hold  Time
parameter   tREF    = 64000000; // Refresh Time
parameter   tRSC    = 2*tCK ;       // 2 * tCK
parameter   tWRa    = tWR     ; // Auto precharge mode
parameter   tWRm    = tWR     ; // Manual precharge mode
parameter   tXSR    = 70          ; // Exit self refresh to ACTIVE command
parameter   CL   =  3       ;   // CAS Latency
`endif



`ifdef T6CL2
// Timing Parameters
parameter   tCK         = 7.5       ;   // Clock Cycle Time
parameter   tRC         = 60            ;// Ref/Act to Ref/Act Command Period
parameter   tRAS    = 42            ;// Active to Precharge Command Period
parameter   tRCD    = 18            ;// Active to Read/Write Command Delay Time
parameter   tCCD    = tCK       ;// Read/Write to Read/Write ( With different Bank) Command Period
parameter   tRP         = 18            ;// Precharge to Active Command Period
parameter   tWR     = 2*tCK ;   // Write Recovery Time
parameter   tCH     = 2         ;// Clock High-Level Width
parameter   tCL         = 2         ;// Clock Low-Level Width
parameter   tAC         = 5.5           ;// Access Time from CLK
parameter   tOH     = 3         ;// Output Data Hold Time
parameter   tHZ     = 6.0       ;   // Output Data High Impedance Time Max
parameter   tLZ         = 0         ;// Output Data Low Impedance Time
parameter   tSB_min = 0         ;// Power Down Mode Entry Time Min
parameter   tSB_max = 6         ;// Power Down Mode Entry Time Max
parameter   tDS         = 1.5     ;     // Data-in Setup Time
parameter   tDH     = 1.0   ;   // Data-in Hold Time
parameter   tAS         = 1.5     ;     // Addr, Bs Setup Time
parameter   tAH         = 1.0     ;     // Addr, Bs Hold Time
parameter   tCKS    = 1.5     ;     // CKE Setup Time
parameter   tCKH    = 1.0     ;     // CKE Hold  Time
parameter   tCMS    = 1.5     ;     // Command Setup Time
parameter   tCMH    = 1.0       ;   // Command Hold  Time
parameter   tREF    = 64000000; // Refresh Time
parameter   tRSC    = 2*tCK ;       // 2 * tCK
parameter   tWRa    = tWR     ; // Auto precharge mode
parameter   tWRm    = tWR     ; // Manual precharge mode
parameter   tXSR    = 72          ; // Exit self refresh to ACTIVE command
parameter   CL      = 2         ;// CAS Latency
`endif

`ifdef T6CL3
// Timing Parameters
parameter   tCK         =6.0      ;     // Clock Cycle Time
parameter   tRC         = 60            ;// Ref/Act to Ref/Act Command Period
parameter   tRAS    = 42            ;// Active to Precharge Command Period
parameter   tRCD    = 18            ;// Active to Read/Write Command Delay Time
parameter   tCCD    = tCK       ;// Read/Write to Read/Write ( With different Bank) Command Period
parameter   tRP         = 18            ;// Precharge to Active Command Period
parameter   tWR     = 2*tCK ;   // Write Recovery Time
parameter   tCH     = 2         ;// Clock High-Level Width
parameter   tCL         = 2         ;// Clock Low-Level Width
parameter   tAC         = 5.0           ;// Access Time from CLK
parameter   tOH     = 3         ;// Output Data Hold Time
parameter   tHZ     = 5.0       ;   // Output Data High Impedance Time Max
parameter   tLZ         = 0         ;// Output Data Low Impedance Time
parameter   tSB_min = 0         ;// Power Down Mode Entry Time Min
parameter   tSB_max = 6         ;// Power Down Mode Entry Time Max
parameter   tDS         = 1.5     ;     // Data-in Setup Time
parameter   tDH     = 1.0   ;   // Data-in Hold Time
parameter   tAS         = 1.5     ;     // Addr, Bs Setup Time
parameter   tAH         = 1.0     ;     // Addr, Bs Hold Time
parameter   tCKS    = 1.5     ;     // CKE Setup Time
parameter   tCKH    = 1.0     ;     // CKE Hold  Time
parameter   tCMS    = 1.5     ;     // Command Setup Time
parameter   tCMH    = 1.0       ;   // Command Hold  Time
parameter   tREF    = 64000000; // Refresh Time
parameter   tRSC    = 2*tCK ;       // 2 * tCK
parameter   tWRa    = tWR     ; // Auto precharge mode
parameter   tWRm    = tWR     ; // Manual precharge mode
parameter   tXSR    = 72          ; // Exit self refresh to ACTIVE command
parameter   CL   =  3       ;   // CAS Latency
`endif





`ifdef T75CL2
// Timing Parameters
parameter   tCK         =10     ;   // Clock Cycle Time
parameter   tRC         =65         ;// Ref/Act to Ref/Act Command Period
parameter   tRAS    =45         ;// Active to Precharge Command Period
parameter   tRCD    =20         ;// Active to Read/Write Command Delay Time
parameter   tCCD    =tCK        ;// Read/Write to Read/Write ( With different Bank) Command Period
parameter   tRP         =20         ;// Precharge to Active Command Period
parameter   tWR     =2*tCK  ;   // Write Recovery Time
parameter   tCH     = 2.5       ;   // Clock High-Level Width
parameter   tCL         = 2.5       ;   // Clock Low-Level Width
parameter   tAC          = 6        ;   // Access Time from CLK
parameter   tOH     =3          ;// Output Data Hold Time
parameter   tHZ     =6          ;// Output Data High Impedance Time Max
parameter   tLZ         =0          ;// Output Data Low Impedance Time
parameter   tSB_min =0          ;// Power Down Mode Entry Time Min
parameter   tSB_max =7.0            ;// Power Down Mode Entry Time Max
parameter   tDS         =1.5      ;     // Data-in Setup Time
parameter   tDH     =1.0    ;   // Data-in Hold Time
parameter   tAS         =1.5      ;     // Addr, Bs Setup Time
parameter   tAH         =1.0      ;     // Addr, Bs Hold Time
parameter   tCKS    =1.5      ;     // CKE Setup Time
parameter   tCKH    =1.0      ;     // CKE Hold  Time
parameter   tCMS    =1.5      ;     // Command Setup Time
parameter   tCMH    =1.0        ;   // Command Hold  Time
parameter   tREF    =64000000   ;// Refresh Time
parameter   tRSC    =2*tCK      ;   // 2 * tCK
parameter   tWRa    =tWR        ;// Auto precharge mode
parameter   tWRm    =tWR        ;// Manual precharge mode
parameter   tXSR    =75         ;// Exit self refresh to ACTIVE command
parameter   CL      =2          ;// CAS Latency
`endif

`ifdef T75CL3
// Timing Parameters
parameter   tCK         =7.5        ;   // Clock Cycle Time
parameter   tRC         =65         ;// Ref/Act to Ref/Act Command Period
parameter   tRAS    =45         ;// Active to Precharge Command Period
parameter   tRCD    =20         ;// Active to Read/Write Command Delay Time
parameter   tCCD    =tCK        ;// Read/Write to Read/Write ( With different Bank) Command Period
parameter   tRP         =20         ;// Precharge to Active Command Period
parameter   tWR     =2*tCK  ;   // Write Recovery Time
parameter   tCH     = 2.5       ;   // Clock High-Level Width
parameter   tCL         = 2.5       ;   // Clock Low-Level Width
parameter   tAC          = 5.4      ;   // Access Time from CLK
parameter   tOH     =3          ;// Output Data Hold Time
parameter   tHZ     =5.5            ;// Output Data High Impedance Time Max
parameter   tLZ         =0          ;// Output Data Low Impedance Time
parameter   tSB_min =0          ;// Power Down Mode Entry Time Min
parameter   tSB_max =7.0            ;// Power Down Mode Entry Time Max
parameter   tDS         =1.5      ;     // Data-in Setup Time
parameter   tDH     =1.0    ;   // Data-in Hold Time
parameter   tAS         =1.5      ;     // Addr, Bs Setup Time
parameter   tAH         =1.0      ;     // Addr, Bs Hold Time
parameter   tCKS    =1.5      ;     // CKE Setup Time
parameter   tCKH    =1.0      ;     // CKE Hold  Time
parameter   tCMS    =1.5      ;     // Command Setup Time
parameter   tCMH    =1.0        ;   // Command Hold  Time
parameter   tREF    =64000000   ;// Refresh Time
parameter   tRSC    =2*tCK      ;   // 2 * tCK
parameter   tWRa    =tWR        ;// Auto precharge mode
parameter   tWRm    =tWR        ;// Manual precharge mode
parameter   tXSR    =75         ;// Exit self refresh to ACTIVE command
parameter   CL      =3          ;// CAS Latency
`endif






// cmds Operation
parameter   ACT     =0;
parameter   NOP     =1;
parameter   READ    =2;
parameter   WRITE   =3;
parameter   PRECH   =4;
parameter   A_REF   =5;
parameter   BST     =6;
parameter   MRS     =7;

parameter BLE1    =3'b000;
parameter BLE2    =3'b001;
parameter BLE4    =3'b010;
parameter BLE8    =3'b011;
parameter FULL_P  =3'b111;

parameter SEQUEN  =0<<3;
parameter INTERLE =1<<3;

parameter BRBW =  0<<9;
parameter BRSW =  1<<9;



// for Debug message
parameter Debug =  1;

TCL Script

database -open waves -shm -default

#probe -create -shm -depth all sdram_tb -exclude sdram_tb.uut
#probe -create -shm sdram_tb.clk_i

#set COMMENTED_OUT {

probe -create -all -depth all -shm

probe -create -unpacked 41944304 sdram_tb.uut.Bank0
probe -create -unpacked 41944304 sdram_tb.uut.Bank1
probe -create -unpacked 41944304 sdram_tb.uut.Bank2
probe -create -unpacked 41944304 sdram_tb.uut.Bank3

#}

run

database -close waves

Commands

xrun -64bit -enable_psc_opt +access+rwc +define+T6CL3+BL8 -input setup_probe.tcl W9825G6KH.nc.vp config_pkg.sv sm.sv top.sv sdram_tb.sv

simvision waves.shm/

XCELIUM Simulations

XCELIUM Waveforms

Demo / Simulation

Questions and Answers

Thanks for Watching

Want to contribute to the sorting accelerator?
- https://github.com/gmejiamtz/sorting_accelerator
Want to contribute to a repository of C programs for the PicoRV32?
- https://github.com/gmejiamtz/picorv32i_programs
Want to make your own project on the ULX3S or another ECP5 FPGA?
- https://github.com/gmejiamtz/ecp5-project-template