CSE 185E Poster Presentation | Gary A. Mejia-Martinez

My poster is on logic block architecture for CSE 185 - Technical Writing for Engineers. I go over how muxes are able to create any boolean function and how flip flops remember data. It ends with a basic discussion on hardware synthesis of HDLs to mapping onto logic blocks of an FPGA.

Today I presented my poster for CSE 185. It rained today but thankfully I stashed my poster in the CSE 125 lab room yesterday. I got a spot in room 180 next to a couple of familiar faces. The dude to my left was the leader of Formula Slug and the dude to my right had the same name as my linear circuits professor. As I was setting up some student already wanted to see my presentation. He was very engaged with the topic of FPGAs and wanted to see their capabilities compared to general purpose processors. Overall I had a great time until it came for grading. My placement in the room made me the last person to be graded as TAs walked around the room to watch presentations. I had a good graded presentation too! My TA knew what Yosys was and had some familiarity with FPGAs so I good engagement to work with. I have the poster saved as a pdf here!