CV
My CV and Resume
Basics
| Name | Gary Mejia Martinez |
| Label | Computer Scientist and Engineer |
| gmejiama@ucsc.edu | |
| Url | https://gmejiamtz.github.io |
| Summary | A growing computer scientist and engineer looking forward to new opportunties. |
Work
- 2020.09 -
CSE Undergraduate Student
Univesity of California, Santa Cruz
Researching new algorithms for improving productivity in hardware design flows
- Electronic Design Automation
- VLSI/FPGA
- Hardware/Software Co-Design
Education
-
2020.09 - Bachelor's of Science
University of California, Santa Cruz
Computer Science and Engineering
- Logic Design with Verilog
- VLSI Digital Logic
- Open Source Hardware Design
- Agile Hardware Design
- Advanced Operating Systems
- Embedded Systems Design
Skills
| Verilog/SystemVerilog | |
| Finite State Machines | |
| UVM Testbenches | |
| Object-Oriented SystemVerilog |
Languages
| English | |
| Native speaker |
| Spanish | |
| Native |
Interests
| Digial Logic Design | |
| SystemVerilog/Verilog | |
| Formal Verification | |
| Memory Design | |
| HDL Compilers | |
| FPGA/ASIC |
Projects
- 2023.05 - 2023.06
Read Only Memory Verilog Model
OpenROM, a subset of OpenRAM (memory compiler), needed a Verilog behavioral model to faciliate testing. Using Python, created a script that wrote a Verilog testbench for a read only memory. Using iVerilog and GTKWave, this behavorial model read 1 bit data and 8 bit data.
- OpenRAM
- Python
- Verilog